16 – Blind and buried vias

Blind and buried vias primarily occur in the case of high package densities and complex PCBs. Blind and buried vias are required due to insufficient space for routing signal layers or for linking to various supply voltages in the interior of the PCB layout.

Depending on the application and space, blind and buried vias can be drilled mechanically or by using lasers. The various possibilities will be shown using the example of a 6-layer multilayer.

16.1 – SBU sequential built-up multilayer

In case of an SBU multilayer, the PCB is constructed from the inside out, layer by layer. Starting from one core, each additional layer is pressed on using a prepreg, structured and, if necessary, drilled and connected.
In case of a 6-layer multilayer, two press-moulding procedures and – depending on the combination of blind and buried vias – up to 3 galvanic cycles will be required.

Solder resist varnish	Solder resist varnish	20 µm	Top
galvanic copper (stage 3)	Copper plating	20 µm
Copper foil	Copper	18 µm
Prepreg	Prepreg	60 µm
galvanic copper (stage 2)	Copper plating	20 µm	Layer 2
Copper foil	Copper	18 µm
Prepreg	Prepreg	60 µm
galvanic copper (stage 1)	Copper plating	20 µm	Layer 3
FR4 core	Copper	18 µm
	FR4	1,2 mm
	Copper	18 µm
galvanic copper (stage 1)	Copper plating	20 µm	Layer 4
Prepreg	Prepreg	60 µm
Copper foil	Copper	18 µm
galvanic copper (stage 2)	Copper plating	20 µm	Layer 5
Prepreg	Prepreg	60 µm
Copper foil	Copper	18 µm
galvanic copper (stage 3)	Copper plating	20 µm	Bottom
Solder resist varnish	Solder resist varnish	20 µm

16.2 – Structure with several cores

Normally, 2 cores are used in the standard 6-layer multilayer structure, and are pressed in a single procedure with the outer layers. In case of blind and buried vias, the multilayer can be made with 3 cores. Then only 2 galvanic cycles are required, even with blind and buried vias.

If blind vias are drilled mechanically and not produced as throughplating in the core (e.g. in the case of blind vias from the top to layer 3),
the layers below must have a minimum spacing of 0,2 mm in order not to come incontact with by the drill. Alternatively, there may be a free position on the layers in the layout below.

Solder resist varnish	Solder resist varnish	20 µm
galvanic copper (stage 2)	Copper plating	20 µm	Top
galvanic copper (stage 1)	Copper plating	20 µm
FR4 core	Copper	18 µm
	FR4	0,3 mm
	Copper	18 µm
galvanic copper (stage 1)	Copper plating	20 µm	Layer 2
Prepreg	Prepreg	0,2 mm
galvanic copper (stage 1)	Copper plating	20 µm	Layer 3
FR4 core	Copper	18 µm
	FR4	0,3 mm
	Copper	18 µm
galvanic copper (stage 1)	Copper plating	20 µm	Layer 4
Prepreg	Prepreg	0,2 mm
galvanic copper (stage 1)	Copper plating	20 µm	Layer 5
FR4 core	Copper	18 µm
	FR4	0,3 mm
	Copper	18 µm
galvanic copper (stage 1)	Copper plating	20 µm
galvanic copper (stage 2)	Copper plating	20 µm	Bottom
Solder resist varnish	Solder resist varnish	20 µm

Design rules
• Blind / buried vias (laser drilled): 0,1 mm
   • Insulation (depth): 0,06 – 0,1 mm
   • Annular ring (circumferential): > 0,1 mm
• Buried vias (mechanically drilled): 0,15 – 0,3 mm
   • Insulation (depth): depending on the aspect ratio 1:8
• Blind vias (mechanically drilled): 0,15 – 0,2 mm
   • above 0,4 mm, HP (hole plugging) is required.
   • Insulation (depth): 0,15 – 0,2 mm
   • Annular ring (circumferential): > 0,125 mm

Note: The two variants shown are only examples. Differences are possible due to special layer structures, technology, etc. and must be tested in individual cases.
The listed annular rings of at least 0,1 mm are only possible after prior inspection of the data. An annular ring of at least 0,125 mm should sensibly be used, in order to guarantee safe production. The aspect ratio AR (ratio drill-hole diameter/depth) for buried vias must be 1:8 and for blind vias 1:1.